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71M6533/G/H and 71M6534/H Data Sheet
VREF
FDS_6533_6534_004
IAP
IAN
VA
IBP
IBN
VB
ICP
ICN
VC
IDP
IDN
MUX
EQU
MUX_ALT
MUX_DIV
VBIAS
VADC
VREF
VREF_CAL
VREF_DIS
?Σ ADC
CONVERTER
VBIAS
FIR
FIR_LEN
VB_REF
ADC_E
VREF
22
VBAT
TEMP
Figure 4: AFE Block Diagram
1.3
Digital Computation Engine (CE)
The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately
measure energy. The CE calculations and processes include:
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Multiplication of each current sample with its associated voltage sample to obtain the energy per
sample (when multiplied with the constant sample time).
Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between
samples caused by the multiplexing scheme).
90 ° phase shifter (for VAR calculations).
Pulse generation.
Monitoring of the input signal frequency (for frequency and phase information).
Monitoring of the input signal amplitude (for sag detection).
Scaling of the processed samples based on calibration coefficients. Scaling of all samples based on
temperature compensation information.
The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled
by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE
program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the
CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.
For proper operation, the code pass must be completed before the multiplexer cycle ends (see Section
2.2 System Timing Summary ).
The CE program must begin on a 1-KB boundary of the flash address. The I/O RAM register CE_LCTN[7:0]
defines which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at
1024* CE_LCTN[7:0].
The CE can access up to 4 KB of data RAM (XRAM), or 1024 32-bit data words, starting at RAM address
0x0000.
The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time
slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access.
The MPU can read and write the XRAM shared between the CE and MPU as the primary means of data
communication between the two processors.
Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE.
14
Rev 2
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